<tool command="cougar" envar="1">
	<row>
		<inputfile descr="input file" empty="0" color="#000000" hasgenfiles="1" hasdirfiles="1" hasprjfiles="1" editable="1" type="isinput"/>
		<outputfile descr="output file" empty="0" color="#000000" editable="1" addtogenfiles="1" type="isoutput"/>
	</row>
	<row>
		<note descr="* the input and output files must have extension" color="#FF0000"/>
	</row>	
	<options>
		<option opt="-t" descr="Notifies a transistor level extraction, the symbolic layout cell is flattened to transistor\nlayout before extraction"/>
		<option opt="-f" descr="The symbolic layout cell is flattened to the catalog level before extraction. Use 'man catal'\nfor detail on the catalog file. If the catalog is empty, or doesn't exist, the netlist is an\ninterconection of transistors, if it isn't, the netlist is an interconection of gates or blocks whose names\nare defined in the catalog"/>
		<option opt="-v" descr="Verbose mode on. Each step of the extraction is displayed on the standard output,\nalong with some statistics"/>
		<option opt="-c" descr="enerates a core file representing the conflictuel net, when cougar detects two external\nconnectors with different names on the same signal, or when it finds two external connectors having\nthe same name but not internally connected to the same net, or when it cannot correctly extract\nan L shaped transistor"/>
		<option opt="-ac" descr="Extract capacitance to ground on losig"/>
		<option opt="-ar" descr="Extract interconnect resistance and capacitance to ground. Value of resistance\nforeach layer can be changed in the RDS file"/>
	</options>
	<command value="command options inputfile outputfile"/>
</tool>
